The present invention generally relates to semiconductor integrated circuits and more particularly to a bipolar integrated circuit having a unit block structure.
In integrated circuits, particularly those used for logic operation, a high operational speed is the essential factor. Because of this reason, logic integrated circuits are usually constructed of bipolar transistors connected to form a so-called emitter coupled logic (ECL). As ECL devices need a substantial, large current for high speed operation, supply of sufficient electric power to each of the logic devices in the integrated circuit becomes increasingly difficult with increasing integration density. Thus, how to supply sufficient electric power to the logic devices in the integrated circuit while maintaining a high integration density is one of the major problems when designing an integrated circuit using the ECL devices.
On the other hand, there is an increasing demand to fabricate a variety of integrated circuits in correspondence to specific purposes though such circuits would be produced in limited number. Such so-called semi-custom made integrated circuits are commonly constructed using a so-called gate array structure shown for example in FIG. 1. Referring to FIG. 1, a number of logic gates having an identical construction and size are arranged on a surface of a semiconductor chip 10 as an array of basic cells 12. The basic cells 12 may be arranged in a plurality of columns 14 or 14a as shown in FIG. 1. Each of the cells 12 has an identical size and construction. The chip, or master slice, having the structure as shown in FIG. 1, is mass-produced and the interconnection between the basic cells 12 is made according to the specific purpose of the integrated circuit which of course changes depending on the type and function required for the integrated circuit.
In such an integrated circuit having a gate array structure, usually not all of the basic cells are used, some of them usually remaining unused. This is because the basic cells are provided on the chip with redundancy in order to secure sufficient number of gates on the chip even when the chip is used for purposes wherein a very large number of basic cells are needed. Thus, the integration density of the gate array structure becomes inevitably lower than the maximum integration density which the integrated circuit is potentially capable of realizing, and associated therewith, there is a problem that the operational speed of the integrated circuit cannot be maximized. Further, there is a problem in that a complex interconnection pattern is needed for connecting the ECL gates in the chip arranged into the basic cells, and associated therewith, there arises a problem in that the average length of interconnection in the chip is increased. Such an increase in the interconnection of course invites a decrease in the operational speed of the integrated circuit. Further, provision of the interconnection becomes increasingly difficult with increasing integration density because of the appearance of a complicated interconnection pattern on the chip during the process of pattern designing, and finding of a path for new interconnections in the region where interconnections are already provided becomes increasingly difficult. Furthermore, such a gate array cannot provide a region for memories or other utilities on the chip, as the chip is provided as the master slice wherein the basic cells are provided so as to cover substantially the entire region of the chip.
On the other hand, there is another concept for designing custom made integrated circuits called the standard cell structure or polycell structure shown in FIG. 2. In this polycell structure, each of the logic devices such as inverters, NOR gates, flip-flops and the like are patterned as polycells 16a each having a standardized, constant height when measured in the Y-direction as shown in FIG. 2. The polycells further have various widths in the X-direction in the drawing, depending on their types and functions. Furthermore, the polycells 16a are assembled in the form of polycell column 16 extending in the X-direction by arranging it so that top edges of adjacent polycells are aligned with each other and bottom edges of adjacent polycells are also aligned with each other as shown in FIG. 2. A number of such polycell columns are formed on the chip, and interconnection between the polycells is made either within the cell columns, or using the space between the cell columns, or crossing one or more cell columns. By using this polycell structure, one can increase the integration density substantially by optimizing the design of the polycells and thereby maximization of the operational speed becomes possible. Note that, in the case of the polycell type integrated circuit, a mask is produced for each of the newly designed integrated circuits and an optimum designing of the integrated circuit becomes possible. Because of this reason, it is also possible to provide a region M for mega-cells, such as memories or other logic units, as desired.
This polycell structure is currently used successfully in the integrated circuits constructed of MOS or CMOS devices. In the MOS or CMOS devices, the electric power consumption is very small and substantially zero in the stationary mode, although there is a compromise to operational speed. In such a low power consumption integrated circuit, no particular problem arises with respect to the feeding of electric power to the devices in the chip and the power conductor for feeding the electric power to each of the polycells may be treated similarly to the interconnection pattern for carrying signals.
FIG. 3 shows a typical example of connecting a power conductor 17, which is commonly connected to a number of polycells 16a in the polycell column 16, to a main power conductor 18 which may be a power terminal pad itself or may be a power conductor connected to a power terminal pad. According to this construction, an electric power supplied externally to the power terminal pad is distributed to a number of polycells 16a, passing through the power conductors 17. As illustrated, each power conductor 17 is extended perpendicularly to the main power conductor 18 and is connected thereto at via-holes 18a. As the current flowing through the power conductor 17 is very small in this case, no particular concern is needed regarding the line width of the power conductor 17 and the numbers and types of the devices included in the polycell column 16 may be variously changed. It should be noted that the phrase "line width" used herein means the width of the conductor measured in the plane of the chip in a direction perpendicular to the elongated direction of the conductor.
When the polycell structure is applied in the case of bipolar integrated circuits including a number of ECL or CML gates, however, there arises a problem of how to supply sufficient electric power to each of the polycells in the integrated circuit. Note that the ECL or CML gate constituting such an integrated circuit needs a substantially large electric current or power for high speed operation. Thus, it is necessary to increase the line width of the power conductors 17 in FIG. 3. When the line width is not increased sufficiently, the current that can be supplied through the power conductors 17 is limited and the number of polycells included in one polycell column has to be decreased. Otherwise, an unacceptable voltage drop may occur in the power conductor 17. When the line width is increased, however, cases occur rather often in which the line width of the power conductors 17 becomes excessively large, reaching a thickness two, three or more times than the height of the polycell column 16. When the line width of the power conductors is increased as to meet the demand for the increased electric power, a substantial area on the chip is occupied by the power conductors and a decrease of the channel area used for interconnection of the ECL gates as well as a decrease of the integration density are invited.
Attempt to overcome this problem by using a multi-level interconnection structure for the power conductors have been generally unsuccessful because of the reason that via-holes, used for inter-layer connection of the polycells to the power conductors, occupy a considerable space. It should be noted that a very large number of power via-holes are needed in order to supply sufficient electric power to any of the ECL gates on the chip. Such a large number of via-holes decreases the possible paths for the routing channels used for passing the interconnection conductors and the degree of freedom when designing the interconnection pattern or "routability" is reduced substantially. It should be noted that the use of regular criss-cross power feed pattern which is used in the gate array structure has also been unsuccessful in the case of the polycell structure as the regularly repeated power conductors do not generally coincide with the corresponding power terminals of the polycells because of the variable width of the polycells in the polycell column.
When the integrated circuit includes the mega-cell region M as in the case of FIG. 2, another problem occurs in that the configuration of the power conductors has to be modified in a region in the vicinity of the mega-cell region M. In this case, the power conductors such as the power conductor 17 shown in FIG. 3 have to be connected to a main power conductor surrounding the region M. As a number of power conductors 17 are connected to such a main power conductor, the main power conductor inevitably occupies a large area. This substantially limits the possible location of the chip where the mega-cell region M can be provided. Such a modification of the power conductor pattern, together with the limitation regarding the possible location of the mega-cells, causes difficulty regarding the automatic and optimum designing of the ECL integrated circuits using the so-called computer-aided design (CAD) process.
Further, when a typical CAD process which combines the channel router process together with the compaction process is applied to the designing of the polycell structure, the obtained polycell column usually extends for almost a full chip length, and because of this, the channel area for interconnection is formed also to extend one full chip length. In such a long channel area, there is a tendency that the degree of channel utilization varies in each part of the channel area such that one part of the channel area is used heavily for interconnection while the other part of the channel area is used less heavily or not used at all. Because of these circumstances, the degree of channel utilization in the conventional polycell type integrated circuit usually remains at about 30-40% and a substantial part of the channel area remains unused or used but insufficiently.